1. Field of the Invention
The present invention relates to methods for manufacturing semiconductor devices and, more particularly, to a method for manufacturing structures having a semiconductor layer on an insulating layer.
2. Description of the Prior Art
Semiconductor microchips or integrated circuits in general are provided in a structure in which an epitaxially grown layer is formed on a silicon substrate and circuits are then formed in the epitaxially grown layer. The silicon substrate and the epitaxially grown layer are joined together to form a pn junction. The resulting capacitance of the pn junction, however, is such that it reduces the operating speed of the device. Accordingly, this structure was not suitable for forming device requiring high-speed operation.
In the last few years, to solve this problem, a way of forming an additional silicon monocrystal layer to overlie the insulating layer on the silicon substrate (Semiconductor on Insulator, or SOI, technique) has been sought. This is to eliminate the pn junction between the semiconductor device formed on the silicon monocrystal layer and the silicon substrate, by insulating the silicon monocrystal layer from the silicon substrate.
FIG. 1 illustrates the conventional SOI technique using the ELO (Epitaxial Lateral Overgrowth) method ("Lateral Epitaxial Overgrowth of Silicon on SiO.sub.2," by D. D. Rathman et. al., JOURNAL OF ELECTROCHEMICAL SOCIETY SOLID-STATE SCIENCE AND TECHNOLOGY, October, 1982, p. 2303). First, a silicon dioxide layer 4 is grown on top of a semiconductor substrate 2. Then, the silicon dioxide layer 4 is etched using photoresist to thereby open seed windows 6 (see FIG. 1A). This is followed by selective epitaxial growth of silicon in the longitudinal direction from the seed windows 6, and, subsequently, lateral epitaxial growth, to form an epitaxial layer 8 on the silicon dioxide layer 4 (see FIG. 1B). By these processes, the pn junction between the epitaxial layer 8 and the silicon substrate 2 can be reduced in area to the size of the seed window 6, thus allowing the pn junction capacitance to be reduced and high-speed operation of the device to be realized.
Another method available is the SENTAXY method ("New SOI-Selective Nucleation Epitaxy," by Ryudai Yonehara et. al., Preliminary Bulletin for the 48th Fall Academic Lecture 1987 by the Applied Physics Society, 19p-Q-15, p. 583). In this method, a plurality of crystal-grown silicon nuclei are formed on an insulating layer of silicon dioxide or the like, further effecting epitaxial growth from each of the nuclei. Methods of forming the nuclei which are under discussion include formation of a small-area silicon nitride layer composed of the nuclei, or employment of the FIB (Focused Ion Beam) method. Using this method allows the epitaxial layer and the silicon substrate to be isolated from one another by an oxide layer, which will solve the aforementioned problems.
However, the conventional SOI technique described above would involve the following problem.
In the ELO method shown in FIG. 1, the junction, although reduced indeed, is not wholly eliminated. This would arrest further increase of the operating speed of the device.
In the SENTAXY method, on the other hand, the epitaxial layer and the silicon substrate are isolated from one another, thus overcoming the above problem. However, the SENTAXY method involves differentiation in the plane bearing of the epitaxial layer that grows from each of the nuclei. This differentiation in the plane bearing of the epitaxial layer will cause variation in oxidation rate and other characteristics, with the result that device having desired characteristics cannot be formed uniformly.